1. Field of the Invention
The present invention generally relates to a method of attaching a heat sink to an integrated circuit package (referred to as IC package hereinafter); more specifically, the present invention relates to an improved method of integrally attaching a heat sink to an IC package for enhancing the thermal conductivity of the package.
2. Description of Prior Art
Conventionally, IC packaging is generally related to a process of packaging a semiconductor die comprising the steps of adhering a semiconductor die to the surface of a supporting substrate, connecting the bond pads to the supporting substrate by means of wire bonding, and encapsulating the molding material to protect the semiconductor die from the environmental contaminants.
A conventional IC package such as a dual inline package can have a relatively small number of pin count, where as a more recently developed ball grid array package (referred to as BGA package hereinafter), in comparison, is provided with a larger amount of pin count as show in FIG. 1. Furthermore, in order to meet the popular demand for electronic components of ever-decreasing sizes, a chip size packaging (referred to as CSP hereinafter) was later developed in order to achieve an IC package such that the dimensions of the semiconductor die encapsulated in the package is almost the same as those of the package itself (e.g. within 20% dimensional differences).
FIG. 1 shows a cross sectional view of a semiconductor die suitably encapsulated by a conventional BGA package. The device shown in FIG. 1 comprises a substrate 1, a semiconductor die 3 which is adhered to the top surface of the substrate 1 by an adhesive layer 2, a plurality of metal wires 4 each correspondingly connecting between a bond pad 3a and the substrate 1, a molding material 5 disposed on the substrate 1 for encapsulating both the wafer die 3 and the wires 4, and a plurality of solder balls 6 mounted to the underside of the substrate 1.
Moreover, it is a common conventional practice to attach or mount a heat sink to the surface of the IC package which is necessary for enhancing the thermal conductivity of the IC package. However, since the semiconductor die is encapsulated by a chip size BGA package, it is very difficult to operate a cost effective IC packaging process if the chip size heat sink is to be successfully mounted to the surface of the IC package every time. As a result, some types of IC package do not even include any heat sink in order to reduce the overall packaging cost by circumventing the technology required for mounting the heat sink, which makes the encapsulated semiconductor die especially a die containing high performance circuits, prone to temperature-related damages and lower operating efficiency.
Referring to FIG. 2A through FIG. 2C, the process of mounting a heat sink 13 to the surface of an IC package 10 according to a conventional method is shown, wherein the IC package 10 comprises a substrate 11 and thereon a molding material 12 encapsulating at least a high performance semiconductor die 3 in between.
Conventionally, a plurality of semiconductor dies are disposed by a matrix layout plan on a communal substrate (not shown) in order to be encapsulated collectively by a packaging (CSP) process to form a plurality of IC packages abutting each other in a matrix arrangement. A cutting or separation procedure is then performed to separate the interconnected IC packages into a plurality of individually formed IC packages 10 in which at least a semiconductor die 3 is encapsulated in between a chip-sized molding material 12 and a chip-sized substrate 11, as shown in FIG. 2A. Then, as shown in FIG. 2B, a heat sink 13 having roughly the same cross dimensions as the IC package 10 is attached to the surface of molding material 12. Typically, as shown in FIG. 2C, the heat sink 13 is fastened to the surface of molding material 12 by a plurality of clips 15.
However, as described above, mounting the chip-sized heat sink 13 accurately to the IC package 10 formed by CSP is a process that requires a high mounting precision, which can adversely increase the overall packaging cost and time. Therefore, due to the aforementioned chip size nature of the IC package 10, it is very difficult to control the precision in aligning the heat sink 13 to the IC package 10 while trying to raise the throughput during actual IC packaging practices.